1. Field of the Invention
The present invention relates generally to Liquid-Crystal Display (LCD) devices. More particularly, the invention relates to a LCD device having comparatively long transmission lines for transmitting internal signals, and a method of transmitting signals in the same device.
2. Description of the Related Art
With LCD devices, generally, the controller circuit outputs an image input signal to be displayed, a polarization reverse signal, a horizontal scanning signal, and a vertical scanning signal. The image input signal is taken into the data electrode driver circuit to be synchronized with the horizontal scanning signal. The pixel data signal corresponding to the image input signal thus taken into is polarization-reversed according to the polarization reverse signal and then, it is sent to the respective data electrodes of the LCD panel from the data electrode driver circuit. The vertical scanning signal is taken into the scanning electrode driver circuit. A scanning signal is sent to the scanning electrode driver circuit to be synchronized with the vertical scanning signal by the scanning electrode driver circuit. The pixel data signal is supplied to the specific pixel regions on the panel chosen by the scanning signal, thereby displaying images on the screen of the panel according to the pixel data signal. The data electrode driver circuit comprises a data electrode driver section or sections. The scanning electrode driver circuit comprises a scanning electrode driver section or sections.
FIG. 1 shows the circuit configuration of an example of the prior-art LCD devices of the type described here. This device comprises a LCD panel 1, a controller circuit 2, a gray scale power supply circuit 3, a data electrode driver circuit 4, and a scanning electrode driver circuit 5.
The LCD panel 1 includes a color filter for generating color images by dividing each pixel into a sub-pixel of red (R), a sub-pixel of green (G), and a sub-pixel of blue (B). The panel 1 further includes n data electrodes X1 to Xn (n: a positive integer greater than 2) to be applied with corresponding sub-pixel data signals D, m scanning electrodes Y1 to Ym (m: a positive integer greater than 2) to be applied with corresponding scanning signals V, and sub-pixel regions (not shown) formed at the respective intersections of the data electrodes X1 to Xn and the scanning electrodes Y1 to Ym, The specific sub-pixel regions chosen by the scanning signals V are applied with the corresponding sub-pixel data signals D, thereby displaying color images on the screen (not shown) of the panel 1 according to the signals D.
The controller circuit 2, which is formed by, for example, an ASIC (Application Specific Integrated Circuit), supplies 8-bit red data DR, 8-bit green data DGr and 8-bit blue data DB to the data electrode driver circuit 4. These data DR, DG, and DB are supplied to the circuit 2 from the outside of the LCD device. The circuit 2 generates a horizontal scanning signal PH, a vertical scanning signal PV, and a polarization reverse signal POL, based on a horizontal synchronization signal SH and a vertical synchronization signal SV, and so on supplied from the outside of the LCD device. The polarization reverse signal POL is used for alternating-current (AC) driving the panel 1. The circuit 2 supplies the horizontal scanning signal PH and the polarization reverse signal POL thus generated to the data electrode driver circuit 4 in the voltage mode and at the same time, it supplies the vertical scanning signal PV thus generated to the scanning electrode driver circuit 5 in the voltage mode. Moreover, the circuit 2 supplies a red scale voltage data DGR, a green scale voltage data DGG, and a blue scale voltage data DGB to the gray scale power supply circuit 3, which are used for giving desired gradation to the data DR, DG, and DB through gamma (xcex3) compensation, respectively.
The gray scale power supply circuit 3 comprises three digital-to-analog converter (DAC) circuits 111, 112, and 113 and 54 voltage follower circuits 121 to 1254, as shown in FIG. 2. The DAC circuit 111converts the digital red scale voltage data DGR to 18 analog red scale voltages VR0 to VR17 and then, the circuit 111 supplies the voltages VR0 to VR17 to the voltage follower circuits 121 to 1218, respectively. Similarly, the DAC circuit 112 converts the digital green scale voltage data DGG to 18 analog green scale voltages VG0 to VG17 and then, the circuit 112 supplies the voltages VG0 to V17 to the voltage follower circuits 1219 to 1236, respectively. The DAC circuit 113 converts the digital blue scale voltage data DGB to 18 analog blue scale voltages VB0 to VB17 and then, the circuit 113 supplies the voltages VB0 to VBB17 to the voltage follower circuits 1237 to 1254, respectively. The analog red scale voltages VR0 to VR17, the analog green scale voltages VG0 to VG17, and the analog blue scale voltages VB0 to VB17 are used for xcex3-compensation to the red data DR, green data DG, and blue data DB, respectively. The voltage follower circuits 121 to 1254 receive the analog red, green, and blue scale voltages VR0 to VR17, VG0 to VG17, or VB0 to VB17 at high input impedance, respectively, and outputs them to the data electrode driver circuit 4 at low output impedance.
The data electrode driver circuit 4 comprises k (k: a natural number) data electrode driver sections 4l to 4k. Each of the sections 4l to 4k applies the specific xcex3-compensation to the red, green, and blue data DR, DG, and/or DE based on the red, green, and blue scale voltages VR0 to VR17, VG0 to VG17, and/or VB0 to VB17 to thereby give gradation thereto. Then, the circuit 4 converts the red, green, and blue data DR, DG, and/or DB thus compensated to 384 sub-pixel data signals D and then, outputs the signals D to the data electrodes X1 to Xn on the panel 1.
For example, if the panel 1 is designed for the SXGA (Super extended Graphics Array) resolution or mode, the panel 1 has 1280 pixels (horizontal)xc3x971024 pixels (vertical) in total. In this case, the count of the sub-pixels is 3840 pixels (horizontal)xc3x971024 pixels (vertical), because each pixel is formed by three sub-pixels, i.e., a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Here, (3840 pixels)/(384 data signals)=10 (pixels/data signal). Thus, the total number of the data electrode driver sections is 10; i.e., k=10. This means that the data electrode driver circuit 4 comprises 10 data electrode driver sections 41 to 410. The following explanation is made under the condition described here.
The data electrode driver sections 41 to 410 have the same circuit configuration as each other except for the suffixes of the respective elements and the respective signals. Thus, only the section 41 is explained below.
The data electrode driver section 41 of the data electrode driver circuit 4 comprises three multiplexer (MPX) circuits 131 to 133, three 8-bit DAC (Digital-to-Analog Converter) circuits 141 to 143, and 384 voltage follower circuits 151 to 15384, as shown in FIG. 3.
The MPX circuit 131 receives the red scale voltages VR0 to VR17 from the gray scale power supply circuit 3 and then, alternately supplies the set of the red scale voltages VR0 to VR8 or the set of the red scale voltages VR9 to VR17 to the DAC circuit 141 according to the polarization reverse signal POL from the controller circuit 2. Similarly, the MPX circuit 132 receives the green scale voltages VG0 to VG17 from the power supply circuit 3 and then, alternately supplies the set of the green scale voltages VG0 to VG8 or the set of the green scale voltages VG9 to VG17 to the DAC circuit 142 according to the polarization reverse signal POL. The MPX circuit 133 receives the blue scale voltages VB0 to VB17 from the power supply circuit 3 and then, alternately supplies the set of the blue scale voltages VB0 to VB8 or the set of the blue scale voltages VB9 to VB17 to the DAC circuit 143 according to the polarization reverse signal POL.
The DAC circuit 141 applies the specific xcex3-compensation to the 8-bit red data DR from the controller circuit 2 based on the set of the red scale voltages VR0 to VR8 or the set of the red scale voltages VR9 to VR17 from the MPX circuit 131, thereby giving gradation to the red data DR, Moreover, the circuit 141 converts the digital red data DR thus compensated to analog red data signals and then, supplies them to the corresponding voltage follower circuits 151, 154, 157, . . . , and 15382. Similarly, the DAC circuit 142 applies the specific xcex3-compensation to the 8-bit green data DG from the controller circuit 2 based on the set of the green scale voltages VG0 to VG8 or the set of the green scale voltages VG9 to VG17 from the MPX circuit 132, thereby giving gradation to the green data DG. Moreover, the circuit 142 converts the digital green data DG thus compensated to analog green data signals and then, supplies them to the corresponding voltage follower circuits 152, 155, 158, . . . , and 15383. The DAC circuit 143 applies the specific xcex3-compensation to the 8-bit blue data DB from the controller circuit 2 based on the set of the blue scale voltages VB0 to VB8 or the set of the blue scale voltages VB9 to VB17 from the MPX circuit 133, thereby giving gradation to the blue data DB. Moreover, the circuit 143 converts the digital blue data DB thus compensated to analog blue data signals and then, supplies them to the corresponding voltage follower circuits 153, 156, 159, . . . , and 15384.
The voltage follower circuits 151 to 15384 receive the corresponding red, green, and blue data signals at high input impedance and then, they send them to the corresponding data electrodes X1 to Xn at low output impedance as the sub-pixel data signals D.
The scanning electrode driver circuit 5 generates the scanning signals V to be synchronized with the vertical scanning signal PV sent from the controller circuit 2. Then, the circuit 5 supplies the scanning signals V thus generated to the corresponding scanning electrodes Y1 to Ym.
The controller circuit 2 and the gray scale power supply circuit 3 are mounted on the printed wiring board (PWB) 16, as shown in FIG. 4. The ten data electrode driver circuits 41 to 410 are respectively mounted on ten carrier tapes that connect electrically the PWB 16 to the panel 1, thereby forming ten tape carrier packages (TCPs) 171 to 1710. The PWB 16 is attached to the top of the backlight unit 18, as shown in FIG. 5. The unit 18, which has an approximately wedge-shaped cross section, is located on the rear side of the panel 1. The unit 18 comprises a point source of light (e.g., a white lamp) or a linear source of light (e.g., a fluorescent lamp), and an optical diffuser for diffusing the light from the light source to thereby form a planar light source. The unit 18 is used to illuminate the back of the panel 1 uniformly, because the panel 1 itself does not emit light.
With the prior-art LCD device of FIG. 1, as shown in FIG. 6, the polarization reverse signal POL and the horizontal scanning signal PH, which are outputted from the controller circuit 2 in parallel, have their active mode periods at different timings. Specifically, when the horizontal scanning signal PH is in its active mode (i.e., in the logic high level), the polarization reverse signal POL is not in its active mode but is in its invalid state. On the other hand, when the polarization reverse signal POL is in its active mode, the horizontal scanning signal PH is not in its active mode.
The red scale voltages VR0 to VR17, which are supplied from the gray scale power supply circuit 3, are inputted into the MPX circuit 13, to be synchronized with the horizontal scanning signal PH. Thereafter, the set of the red scale voltages VR0 to VR8 or the set of the red scale voltages VR9 to VR17 are alternately supplied to the DAC circuit 141 according to the polarization reverse signal POL. Similarly, the green scale voltages VG0 to VG17, which are supplied from the gray scale power supply circuit 3, are inputted into the MPX circuit 132 to be synchronized with the horizontal scanning signal PH. Thereafter, the set of the green scale voltages VG0 to VG8 or the set of the green scale voltages VG9 to VG17 are alternately supplied to the DAC circuit 142 according to the polarization reverse signal POL. The blue scale voltages VB0 to VB17, which are supplied from the gray scale power supply circuit 3, are inputted into the MPX circuit 133 to be synchronized with the horizontal scanning signal PH. Thereafter, the set of the blue scale voltages VB0 to VB8 or the set of the blue scale voltages VB9 to VB17 are alternately supplied to the DAC circuit 143 according to the polarization reverse signal POL.
The 8-bit red data DR, which are supplied from the controller circuit 2 and inputted into the DAC circuit 141, are subjected to the xcex3-compensation in the DAC circuit 141 based on the set of the red scale voltages VR0 to VR0 or the set of the red scale voltages VR9 to VR17, thereby giving the gradation to the data DR. At the same time as this, the red data DR are converted to the analog red data signals. The analog red data signals thus obtained are supplied to the corresponding voltage follower circuits 151, 154, 157, . . . , and 15382. Similarly, the 8-bit green data DG, which are supplied from the controller circuit 2 and inputted into the DAC circuit 142, are subjected to the xcex3-compensation in the DAC circuit 142 based on the set of the green scale voltages VG0 to VG8 or the set of the green scale voltages VG9 to VG17, thereby giving the gradation to the data DG. At the same time as this, the green data DG are converted to the analog green data signals. The analog green data signals thus obtained are supplied to the corresponding voltage follower circuits 152, 155, 158, . . . , and 15383. The 8-bit blue data DB, which are supplied from the controller circuit 2 and inputted into the DAC circuit 143, are subjected to the xcex3-compensation in the DAC circuit 143 based on the set of the blue scale voltages VB0 to VB8 or the set of the blue scale voltages VB9 to VB17, thereby giving the gradation to the data DB. At the same time as this, the blue data DB are converted to the analog blue data signals. The analog blue data signals thus obtained are supplied to the corresponding voltage follower circuits 153, 156, 159, . . . , and 15384.
The analog red, green, and blue data signals thus obtained are sent to the corresponding data electrodes X1 to Xn as the sub-data signals D.
The vertical scanning signal PV is supplied to the scanning electrode driver circuit 5 from the controller circuit 2. The scanning signals V are generated and outputted by the circuit 5 to the scanning electrodes Y1 to Ym to be synchronized with the signal PV. In the panel 1, the sub-pixel data signals D are respectively supplied to the specific sub-pixel regions chosen by the scanning signals V, thereby displaying color images on the screen (not shown) of the panel 1 according to the sub-pixel data signals D thus supplied.
With the above-described prior-art LCD device, there are the following problems.
The horizontal and vertical scanning signals PH and PV, the polarization reverse signal POL, the red, green, and blue data DR, DG, and DB, the red scale voltages VR0 to VR17, the green scale voltages VG0 to VG17, and the blue scale voltages VB0 to VB17 are all transmitted in the voltage mode. Therefore, if the prior-art LCD device is designed to be comparatively large, the transmission lines for these signals or data will be comparatively long. In this case, the signals or data are likely to be affected by the distributed constants or parameters (e.g., distributed capacitance, inductance, and resistance) in the transmission lines and thus, the signals and/or data thus transmitted may have xe2x80x9cphase rotationxe2x80x9d in their high-frequency regions. As a result, a problem that the image quality degrades may occur.
Moreover, since the distributed capacitors of the transmission lines are charged and discharged responsive to the voltage change of the respective signals, high-frequency noises are generated. These noises tend to affect EMI (Electro-Magnetic Interference) to other electronic equipment. This is another problem.
Furthermore, each of the horizontal and vertical scanning signals PH and PV requires a transmission line. The polarization reverse signal POL requires a transmission line. The 8-bit red data DR require eight transmission lines. The 8-bit green data DG require eight transmission lines. The 8-bit blue data DB require eight transmission lines. The red scale voltages VR0 to VR17 require eighteen transmission lines. The green scale voltages VG0 to VG17 require eighteen transmission lines. The blue scale voltages VB0 to VB17 require eighteen transmission lines. Therefore, if the PWB 16 and/or the TCPs 171 to 1710 are designed to be small in size, a problem that required transmission lines are difficult or unable to be formed as desired will occur. Thus, it is necessary that the count of the transmission lines required is possibly decreased to cope with the tendency to make the LCD device more compact.
Accordingly, an object of the present invention is to provide a LCD device having a decreased number of required transmission lines, and a method of transmitting signals in the device.
Another object of the present invention is to provide a LCD device that prevents or suppresses the phase rotation and noises in the high-frequency regions of the signals to be transmitted in the device, and a method of transmitting signals in the device.
Still another object of the present invention is to provide a LCD device that avoids the EMI to other electronic equipment, and a method of transmitting signals in the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the invention, a LCD device is provided, which comprises:
a LCD panel having data electrodes for receiving pixel data signals, scanning electrodes for receiving scanning signals, and pixel regions located at intersections of the data electrodes and the scanning electrodes;
part of the pixel regions being chosen by the scanning signals;
the pixel data signals being applied to the part of the pixel regions, displaying images corresponding to the pixel data signals applied;
a data electrode driver circuit for receiving an image input signal to be synchronized with a horizontal scanning signal, for polarization-reversing the pixel data signals corresponding to the image input signal based on a polarization reverse signal, and for transmitting the pixel data signals thus polarization-reversed to the data electrodes of the panel;
a scanning electrode driver circuit for transmitting scanning signals to the scanning electrodes of the panel to be synchronized with a vertical scanning signal; and
a controller circuit for outputting the image input signal, the polarization reverse signal, the horizontal scanning signal, and the vertical scanning signal;
wherein the controller circuit comprises a first interface circuit for receiving the polarization reverse signal and the horizontal scanning signal in parallel in such a way that the polarization reverse signal and the horizontal scanning signal have their active mode periods at different timings, for generating a serial signal from the polarization reverse signal and the horizontal scanning signal, and for transmitting the serial signal to the data electrode driver circuit by way of a transmission line or lines;
and wherein the data electrode driver circuit comprises a second interface circuit for regenerating the polarization reverse signal and the horizontal scanning signal in parallel from the serial signal.
With the LCD device according to the first aspect of the invention, the first interface circuit is provided in the controller circuit. The first interface circuit receives the polarization reverse signal and the horizontal scanning signal in parallel in such a way that the polarization reverse signal and the horizontal scanning signal have their active mode periods at different timings. Further, the first interface circuit generates the serial signal from the polarization reverse signal and the horizontal scanning signal, and transmits the serial signal to the data electrode driver circuit by way of the transmission line or lines.
Moreover, the second interface circuit is provided in the data electrode driver circuit. The second interface circuit regenerates the polarization reverse signal and the horizontal scanning signal in parallel from the serial signal.
Accordingly, the total number of required transmission lines can be decreased, which makes it possible to cope with the tendency of making the LCD device more compact.
In a preferred embodiment of the device according to the first aspect of the invention, the device has a configuration that the serial signal is transmitted in a current mode. In this embodiment, the serial signal is transmitted in a current mode and therefore, the phase rotation in the high-frequency regions of the signals to be transmitted in the device can be avoided. This means that the quality of images is improved and at the same time, high-frequency noises can be reduced and the EMI to other electronic equipment can be avoided.
In another preferred embodiment of the device according to the first aspect of the invention, the first interface circuit comprises a parallel-to-serial converter circuit for converting the polarization reverse signal and the horizontal scanning signal transmitted in parallel to a first serial signal voltage; and a voltage-to-current converter circuit for converting the first serial signal voltage to a signal current. The signal current is outputted to the transmission line or lines. The second interface circuit comprises a current-to-voltage converter circuit for converting the signal current to a second signal voltage; and a serial-to-parallel converter circuit for converting the second signal voltage to the polarization reverse signal and the horizontal scanning signal in parallel.
In still another preferred embodiment of the device according to the first aspect of the invention, the data electrode driver circuit comprises at least one data electrode driver section according to a count of the data electrodes.
According to a second aspect of the invention, a method or transmitting signals in a LCD device is provided. The device comprises:
a LCD panel having data electrodes for receiving pixel data signals, scanning electrodes for receiving scanning signals, and pixel regions located at intersections of the data electrodes and the scanning electrodes;
part of the pixel regions being chosen by the scanning signals;
the pixel data signals being applied to the part of the pixel regions, displaying images corresponding to the pixel data signals applied;
a data electrode driver circuit for receiving an image input signal to be synchronized with a horizontal scanning signal, for polarization-reversing the pixel data signals corresponding to the image input signal based on a polarization reverse signal, and for transmitting the pixel data signals thus polarization-reversed to the data electrodes of the panel;
a scanning electrode driver circuit for transmitting scanning signals to the scanning electrodes of the panel to be synchronized with a vertical scanning signal; and
a controller circuit for outputting the image input signal, the polarization reverse signal, the horizontal scanning signal, and the vertical scanning signal.
The controller circuit receives the polarization reverse signal and the horizontal scanning signal in parallel in such a way that the polarization reverse signal and the horizontal scanning signal have their active mode periods at different timings, generates a serial signal from the polarization reverse signal and the horizontal scanning signal, and transmits the serial signal to the data electrode driver circuit by way of a transmission line or lines.
The data electrode driver circuit regenerates the polarization reverse signal and the horizontal scanning signal in parallel from the serial signal.
With the method of transmitting a signal in a LCD device according to the second first aspect of the invention, the controller circuit and the data electrode driver circuit carry out the same operations as those in the LCD device according to the first aspect of the invention. Therefore, it is obvious that the same advantages as those in the device of the first embodiment are obtainable.
In a preferred embodiment of the method according to the second aspect of the invention, the serial signal is transmitted in a current mode. In this embodiment, the phase rotation in the high-frequency regions of the signals to be transmitted in the device can be avoided. This means that the quality of images is improved and at the same time, high-frequency noises can be reduced and the EMI to other electronic equipment can be avoided.
In another preferred embodiment of the method according to the second aspect of the invention, the controller circuit conducts a parallel-to-serial conversion step for converting the polarization reverse signal and the horizontal scanning signal transmitted in parallel to a first serial signal voltage; and a voltage-to-current conversion step for converting the first serial signal voltage to a signal current. The signal current is outputted to the transmission line or lines. The data electrode converter circuits conducts a current-to-voltage conversion step for converting the signal current to a second signal voltage; and a serial-to-parallel conversion step for converting the second signal voltage to the polarization reverse signal and the horizontal scanning signal in parallel.